The IXP1200 chip contains two levels of processors: a general-purpose StrongARM processor and six special-purpose Micro-Engines. Each of the six Micro-Engines supports four hardware contexts, for a total of 24 contexts. The IXP1200 board is connected to a Pentium processor by a PCI bus, resulting in a three-level processor hierarchy.
The IXP1200 is designed to forward minimum-sized IP packets at line speeds. The challenge is how to program it properly to achieve high forwarding rates. The question is how to employ the multiple hardware contexts and other resources on the board to effectively utilize the memory bandwidth. The authors adopt a static resource allocation, which results in a maximum forwarding rate of 2.69Mpps(packets per second). This is not only far below the 21.4Mpps which the Micro-Engines can provide, but also lower than the DRAM bandwidth capacity of 5.45Mpps. Reducing memory contention and unnecessary DRAM access is the key to improve the maximum forwarding rate.
Although 2.69Mpps is not the maximum forwarding rate achievable for the IXP1200, it is higher than the actual network input of the board, which is 1.128Mpps. So 400 cycles are available for additional processing for each 64-byte chunk. Also the StrongARM processor and the Pentium processor have excess cycles for packets. It is another challenge to use the processors' excess capacity to extend router functions while sustaining a certain forwarding rate.
The new hardware for routers such as the IXP1200 network processor doesn't necessarily make it easy to construct a router with extensive services. VERA is a virtual router architecture that hides the hardware details and help map the services to underlying hardware. VERA consists of a router abstraction, a hardware abstraction, and a distributed router operating system. The router operating system bridges the semantic gap between the high-level router abstraction and the low-level hardware abstraction. The authors' main contribution is to identify and motivate design choices in the development of VERA.
The MIT group deal with the difficulty of building routers with extensive
services on regular PCs. They propose Click, an open, extensible, and configurable
router framework. Their work demonstrates that real routers can be built
from small elements. Individual elements implement simple router functions
like packet classification, queuing, or scheduling. Extending a standard
IP router to support dropping policies, fairness among flows, or Differentiated
Services simply requires
adding a couple of elements at the right place. The modularity of Click
is also compatible with good forwarding performance. The Click IP router
achieves a maximum loss-free forwarding rate of 333Kpps on conventional
PC hardware.